The present disclosure relates in general to semiconductor devices, and more particularly, to power grid designs and/or memory devices.
The use of split-word line (SWL) style memory cells, such as are used in embedded static random access memory (EBSRAM), provide several different advantages. These advantages include lithography friendly patterns on critical layers such as poly-1 and metal-1, and a high speed bit-line structure. The high speed bit-line structure is due, in part, to various items, including having a relatively low length-to-width ratio of the bit lines, and having the bit lines on a lower metal layer (i.e., nearer the substrate) with as few level changes as possible.
A problem occurs when having the bit lines on a lower metal layer. For example, a typical design of an SWL memory cell includes a first metal layer (M1) that supports the direct connections to the SWL memory cell devices; a second metal layer (M2) that supports a power supply (e.g., Vcc) and bit lines; and a third metal layer (M3) that supports a power supply (e.g., Vss) and word lines. The second metal layer M2 can be come very crowded due not only to the lines, but to contacts for receiving and connecting to interlayer vias and landing pads to the first metal layer M1.
This crowding problem is exacerbated when a shrink is performed. After a shrink, the landing pad size and/or alignment must be maintained to allow for the required design-rule requirements. Furthermore, issues may arise from lithography capability and misalignment.
What is needed is a new metal layer design that solves one or more of the above-listed problems. Also what is needed is a more robust power grid design.